In the modern society, the amount of digital information is increasing dramatically, which poses an ever increasing demand on processing, transmission, and storage of the information. As driven by this demand, the semiconductor industry (especially the CMOS technique), which is the backbone of the information industry, has been developing rapidly according to Moore's Law and has developed the most rapidly over the past 50 years.
With the rapid development of the CMOS technique, the integration degree of the device on a chip is increasing continuously and the speed of the chip is also becoming faster. To meet the demand regarding the integration degree and speed of the device, Cu interconnection has gradually become popular and replacing the conventional Al interconnection. At the same time, the line width of the interconnection has decreased continuously, and the wiring density has increased. With further decrease in the line width of the Cu interconnection, electron scattering resulting from the grain boundary and surface will lead to significant increase in the resistivity of Cu, which will increase the interconnection delay due to the resistance and capacitance (RC) and reduce the overall performance of the chip.
Device delay and interconnection delay jointly determine the maximum operation frequency of a circuit. As the device decreases continuously in size, the interconnection delay has surpassed the delay of device level, and has become a dominant factor of influencing the operation frequency of the circuit. Especially with the decrease in the line width, the electron transport in Cu wire suffers from a more intensive scattering from the surface and the grain boundary, and the resistivity of a Cu wire with a line width of 100 nm or less increases dramatically, which may greatly affect the performance of the circuit. The use of a low-k dielectric may reduce the parasitic capacitance introduced by the interconnection. However, the application of low-k dielectric is also accompanied with several issues regarding e.g. integration, reliability, and the like. Besides, the dielectric constant of a low-k material will reach its limit around 1.5. It's expected that the approach of depositing Cu by an electrochemical method or CVD and the application of a low-k material may continue to 2020. Nevertheless, the research and development of a post-Cu interconnection technique (comprising an optical interconnection, carbon nano-material interconnection, and the like) is of great urgency.
Graphene is a novel material. In fact, it is a monoatomic layer of graphite, a monolayer thin film with a hexagonal honeycomb lattice plane composed by a monolayer of carbon atoms, and two-dimensional material with a thickness of a carbon atom. In contrast, a graphene nanoribbon is ribbon-shaped graphene, and can be understood as an expanded single-wall carbon nanotube or a patterned graphene structure. Graphene exhibits excellent properties, such as high carrier mobility, high current density, high mechanical strength, high thermal conductivity, and the like.
In addition to the excellent properties of graphene, graphene nanoribbons have their own unique characteristics as follow.
1. They have a high electrical conductivity. It has been reported that the mean free path may amount to several hundred nanometers, and the high electron mobility is about few micrometers. Multi-layer graphite nanoribbons in parallel connection can significantly reduce the resistance, improve the performance, and show under small dimension a much better performance than that of Cu interconnection.
2. They have a superior anti-electromigration performance. The neighboring carbon atoms are bonded by SP2 valence bonds. The mechanical strength and anti-electromigration performance are very excellent. They can withstand a current density of 10E9A/cm2, which is larger than 10E6A/cm2 of Cu.
3. They have an even better thermal conductivity. It is reported that the monolayer graphene has a thermal conductivity of 5300 W/mK. When applied to the interconnection technique, it may have an even better heat dissipating performance, and may improve the interconnection in term of reliability.
4. Depending on the edge state of GNR (grapheme nanoribbon), the resistivity may change from a semiconductor into a conductor. As shown in FIG. 1, a Zigzag edge topology 11 corresponds to a conductor, while the other armchair edge topology 12 corresponds to a semiconductor. Therefore, different applications may be designed with respect to the edge topology.
A carbon nanotube is a tube-shaped carbon molecule. Each carbon atom on the tube is SP2 hybridized, and is bonded with each other by a C—C σ bond, so as to form a hexagonal honeycomb structure as the framework of a carbon nanotube. A pair of p electrons which are not hybridized in each carbon atom form a conjugated π-electron cloud therebetween across the whole carbon nanotube. On the basis of the layer number in the tube, the carbon nanotube can be divided into a single-wall carbon nanotube and a multi-wall carbon nanotube. The nano-tube is very thin in the radius direction and is of nanoscale, while the length of a nanotube can be up to hundreds of micrometer.
The carbon nanotube has superior mechanical and electrical properties, and is also a high potential nano-material for applications in the interconnection technique, especially due to its oriented growth along the catalyst.
The excellent properties of a carbon-based nano-material have gradually drawn attention in the industry. As early as in IEDM2009, Yuji Awano, et al., indicated in a paper that graphene interconnection and carbon nanotube interconnection would be a very potential candidate for the interconnection technique in the post-CMOS time.
In the prior art advanced CMOS technique, the interconnection is generally defined as 3 kinds of levels, i.e., a local interconnection, an intermediate interconnection, and a global interconnection. The local interconnection is a level with a relatively small size, lies in the bottom of the interconnection structure, and comprises several levels like contact, metal1, via1, metal2, via2, and the like. Due to its relatively small size, the local interconnection has a relatively high wiring density, and tends to be affected in term of performance and reliability by parasitic resistance and parasitic capacitance as well as heat dissipation in the Cu interconnection with small size. The intermediate interconnection and the global interconnection have a relatively large size and a relatively low wiring density, and thus are less affected by the small size effect.